? semiconductor components industries, llc, 2010 june, 2010 ? rev. 2 1 publication order number: NB7VQ1006M/d NB7VQ1006M 1.8v / 2.5v 10gbps equalizer receiver with 1:6 differential cml outputs multi ? level inputs w/ internal termination description the NB7VQ1006M is a high performance differential 1:6 cml fanout buffer with a selectable equalizer receiver. when placed in series with a data path operating up to 10 gb/s, the NB7VQ1006M will compensate the degraded data signal transmitted across a fr4 pcb backplane or cable interconnect and output six identical cml copies of the input signal. therefore, the serial data rate is increased by reducing inter ? symbol interference (isi) caused by losses in copper interconnect or long cables. the equalizer enable pin (eqen) allows the in/in inputs to either flow through or bypass the equalizer section. control of the equalizer function is realized by setting eqen; when eqen is set low, the in/in inputs bypass the equalizer. when eqen is set high, the in/in inputs flow through the equalizer. the default state at startup is low. as such, the NB7VQ1006M is ideal for sonet, gige, fiber channel, backplane and other data distribution applications. the differential inputs incorporate internal 50 termination resistors that are accessed through the vt pin. this feature allows the NB7VQ1006M to accept various logic level standards, such as lvpecl, cml or lvds. this feature provides transmission line termination at the receiver, eliminating external components. the outputs have the flexibility of being powered by either a 1.8 v or 2.5 v supply. the NB7VQ1006M is a member of the gigacomm ? family of high performance clock/data products. features ? maximum input data rate > 10 gbps ? maximum input clock frequency > 7.5 ghz ? backplane and cable interconnect compensation ? 225 ps typical propagation delay ? 30 ps typical rise and fall times ? differential cml outputs, 400 mv peak ? to ? peak, typical ? operating range: v cc = 1.71 v to 2.625 v, gnd = 0 v ? internal input termination resistors, 50 ? qfn ? 24 package, 4 mm x 4 mm ? ? 40 c to +85 c ambient operating temperature ? these are pb ? free devices* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. marking diagram* qfn ? 24 mn suffix case 485l http://onsemi.com *for additional marking information, refer to application note and8002/d. see detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. ordering information nb7v q1006m alyw 1 24 a = assembly location l = wafer lot y = year w = work week = pb ? free package (note: microdot may be in either location) eq simplified block diagram
NB7VQ1006M http://onsemi.com 2 figure 1. detailed block diagram of NB7VQ1006M q3 q3 q2 q2 q1 q1 q0 q0 q4 q4 q5 q5 0 1 in vt in eq eqen (equalizer enable) multi ? level inputs lvpecl, lvds, cml cml outputs 50 50 75 k table 1. equalizer enable function eqen function 0 in/in inputs bypass the equalizer section 1 in/in inputs flow through the equalizer section q3 q3 gnd vcc in vt gnd vcco vcco q2 figure 2. qfn ? 24 lead pinout (top view) q2 in eqen vcc 18 12 4 3 5 6 789 11 10 2 1 17 16 15 14 13 19 24 23 22 20 21 exposed pad (ep) q1 q1 q0 q0 gnd q5 q4 q4 q5 gnd NB7VQ1006M
NB7VQ1006M http://onsemi.com 3 table 2. pin description pin name i/o description 1 vcc positive supply voltage for the core logic 2 in lvpecl, cml, lvds input non ? inverted differential clock/data input. (note 1) 3 in lvpecl, cml, lvds input inverted differential clock/data input. (note 1) 4 vt internal 50 termination pin for in and in 5 eqen lvcmos input equalizer enable input; pin will default low when left open (has internal pull ? down resistor) 6 vcc positive supply voltage for the core logic 7 gnd negative supply voltage 8 q5 cml inverted differential output. typically terminated with 50 resistor to v cc . 9 q5 cml non ? inverted differential output. typically terminated with 50 resistor to v cc . 10 q4 cml inverted differential output. typically terminated with 50 resistor to v cc . 11 q4 cml non ? inverted differential output. typically terminated with 50 resistor to v cc . 12 gnd negative supply voltage 13 vcco positive supply voltage for the pre ? amplifier and output buffer 14 q3 cml inverted differential output. typically terminated with 50 resistor to v cc . 15 q3 cml non ? inverted differential output. typically terminated with 50 resistor to v cc . 16 q2 cml inverted differential output. typically terminated with 50 resistor to v cc . 17 q2 cml non ? inverted differential output. typically terminated with 50 resistor to v cc . 18 vcco positive supply voltage for the pre ? amplifier and output buffer 19 gnd negative supply voltage 20 q1 cml inverted differential output. typically terminated with 50 resistor to v cc . 21 q1 cml non ? inverted differential output. typically terminated with 50 resistor to v cc . 22 q0 cml inverted differential output. typically terminated with 50 resistor to v cc . 23 q0 cml non ? inverted differential output. typically terminated with 50 resistor to v cc . 24 gnd negative supply voltage ? ep ? the exposed pad (ep) on the qfn ? 24 package bottom is thermally connected to the die for im- proved heat transfer out of package. the exposed pad must be attached to a heat ? sinking con- duit. the pad is electrically connected to gnd and is recommended to be electrically connected to gnd on the pc board. 1. in the dif ferential configuration when the input termination pin (vt) is connected to a common termination voltage or left op en, and if no signal is applied on in/in , then the device will be susceptible to self ? oscillation. 2. all vcc, vcco and gnd pins must be externally connected to the same power supply voltage to guarantee proper device operation .
NB7VQ1006M http://onsemi.com 4 table 3. attributes characteristics value esd protection human body model machine model > 4 kv > 200 v moisture sensitivity (note 3) level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 244 meets or exceeds jedec spec eia/jesd78 ic latchup test 3. for additional information, see application note and8003/d. table 4. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc , v cco positive power supply gnd = 0 v 3.0 v v i input voltage gnd = 0 v ? 0.5 to v cc + 0.5 v v inpp differential input voltage |in ? in | 1.89 v i in input current through r t (50 resistor) 40 ma i out output current through r t (50 resistor) 40 ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 4) tgsd 51 ? 6 (2s2p multilayer test board) with filled thermal vias 0 lfpm 500 lfpm qfn ? 24 qfn ? 24 37 32 c/w c/w jc thermal resistance (junction ? to ? case) standard board qfn ? 24 11 c/w t sol wave solder pb ? free 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 4. jedec standard multilayer board ? 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
NB7VQ1006M http://onsemi.com 5 table 5. dc characteristics ? cml output v cc = v cco = 1.71 v to 2.625 v; gnd = 0 v t a = ? 40 c to 85 c symbol characteristic min typ max unit power supply current (inputs and outputs open) i cc i cco power supply current, core logic v cc = 2.5v v cc = 1.8v power supply current, outputs v cco = 2.5v v cco = 1.8v 100 85 180 150 115 95 200 175 ma cml outputs (notes 5 and 6) (figure 10) v oh output high voltage v cco = 2.5 v v cco = 1.8 v v cco ? 40 2460 1760 v cco ? 10 2490 1790 v cco 2500 1800 mv v ol output low voltage v cco = 2.5v v cco = 2.5v v cco = 1.8v v cco = 1.8v v cco ? 600 1900 v cco ? 525 1275 v cco ? 500 2000 v cco ? 425 1375 v cco ? 400 2100 v cco ? 300 1500 mv data/clock inputs (in, in ) (note 7) (figures 6 & 7) v ihd differential input high voltage 1100 v cc mv v ild differential input low voltage gnd v cc ? 100 mv v id differential input voltage (v ihd ? v ild ) 100 1200 mv i ih input high current ? 150 30 +150 a i il input low current ? 150 ? 40 +150 a control inputs (eqen) v ih input high voltage v cc x 0.65 v cc mv v il input low voltage gnd v cc x 0.35 mv i ih input high current ? 150 25 +150 a i il input low current ? 150 10 +150 a termination resistors r tin internal input termination resistor 45 50 55 r tout internal output termination resistor 45 50 55 note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. cml outputs loaded with 50 to v cc for proper operation. 6. input and output parameters vary 1:1 with v cc/ v cco . 7. v ihd , v ild, v id and v cmr parameters must be complied with simultaneously.
NB7VQ1006M http://onsemi.com 6 table 6. ac characteristics v cc = v cco = 1.71 v to 2.625 v; gnd = 0 v t a = ? 40 c to 85 c (note 8) symbol characteristic min typ max unit f data maximum operating input data rate 10 gbps f max maximum input clock frequency v cc = 2.5v v cc = 1.8v 7.5 6.5 ghz v outpp output voltage amplitude eqen = 0 or 1 f in 5.0 ghz v cc = 2.5v (see figures 4, note 9) f in 7.5 ghz v cc = 2.5v f in 5 ghz v cc = 1.8v f in 6.5 ghz v cc = 1.8v 275 225 225 200 440 360 360 315 mv v cmr input common mode range (differential configuration, note 10) (figure 8) 1050 v cc ? 50 mv t plh , t phl propagation delay to output differential, in/in to qn/qn 170 225 315 ps t plh tc propagation delay t emperature coefficient ? 40 c to +85 c 30 fs/ c t dc output clock duty cycle 48 50 52 % t skew duty cycle skew (note 11) within device skew (note 12) device to device skew (note 13) 0.15 10 20 1 25 40 ps t jitter random clock jitter rj(rms), 1000 cycles (note 14) eqen = 1f in 5.0 ghz 5 ghz f in 7.5 ghz deterministic jitter (dj) (note 15) eqen = 1, fr4 = 12?, 10 gbps v cc = 2.5 v v cc = 1.8 v 0.2 0.2 3 3 0.7 1.2 40 20 ps v inpp input voltage swing (differential configuration) (note 16) (figure 6) 100 1200 mv t r , t f output rise/fall times qn/qn , (20% ? 80%) 30 65 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. measured using a 400 mv source, 50% duty cycle 1ghz clock source. all outputs must be loaded with external 50 to v cco . input edge rates 40 ps (20% ? 80%). 9. output voltage swing is a single ? ended measurement operating in differential mode. 10. v cmr min varies 1:1 with gnd, v cmr max varies 1:1 with v cc . the v cmr range is referenced to the most positive side of the differential input signal. 11. duty cycle skew is measured between differential outputs using the deviations of the sum of t pw ? and t pw + @ 5 ghz. 12. within device skew compares coincident edges. 13. device to device skew is measured between outputs under identical transition 14. additive clock jitter with 50% duty cycle clock signal. 15. additive peak ? to ? peak jitter with input nrz data at prbs23. 16. input voltage swing is a single ? ended measurement operating in differential mode, with minimum propagation change of 25 ps. figure 3. output voltage amplitude (v outpp ) vs. input frequency (f in ) at ambient temperature (typ), (eqen = 0) f in , clock input frequency (ghz) output voltage amplitude (mv) 500 450 400 350 300 250 012 8 7 6 5 4 3 figure 4. input structure 50 50 v t v cc in in q output amplitude (mv) v cc = 2.5 v q output amplitude (mv) v cc = 1.8 v
NB7VQ1006M http://onsemi.com 7 v ild(max) v ihd(max) v ihd(typ) v ild(typ) v ihd(min) v ild(min) v cmr gnd v id = v ihd ? v ild v cc in in q q t plh t phl v outpp = v oh (q) ? v ol (q) v inpp = v ih (in) ? v il (in) figure 5. differential inputs driven differentially figure 6. ac reference measurement v ihd v ild v id = |v ihd(in) ? v ild(in)| in in in in v cm(min) figure 7. v cmr diagram v cm(max) driver device receiver device qd figure 8. typical termination for cml output driver and device evaluation q d v cco 50 50 z = 50 z = 50 dut
NB7VQ1006M http://onsemi.com 8 figure 9. typical cml output structure and termination v cco 50 50 16 ma 50 50 v cc (receiver) gnd figure 10. alternative output termination v cco 50 50 16 ma 100 gnd application information figure 11. typical nb7vq1006 equalizer application and interconnect with prbs23 pattern at 7.0 gbps q q vt in v cc in driver dj1 dj2 dj3 fr4 ? 12 inch backplane NB7VQ1006M equalizer
NB7VQ1006M http://onsemi.com 9 lvpecl driver v ccx gnd z o = 50 v t z o = 50 NB7VQ1006M in 50 50 in gnd figure 12. lvpecl interface lvds driver v cc gnd z o = 50 v t = open z o = 50 NB7VQ1006M in 50 50 in gnd figure 13. lvds interface v cc v cc cml driver v cc gnd z o = 50 v t = v cc z o = 50 NB7VQ1006M in 50 50 in gnd v cc figure 14. standard 50 load cml interface differential driver v cc gnd z o = 50 vt = v refac * z o = 50 NB7VQ1006M in 50 50 in gnd v cc figure 15. capacitor ? coupled differential interface (vt connected to external v refac ) *v refac bypassed to ground with a 0.01 f capacitor v ccx = 2.5 v, v t = gnd v ccx = 3.3 v, v t = 70 to gnd ordering information device package shipping ? NB7VQ1006Mmng qfn ? 24 (pb ? free) 92 units / rail NB7VQ1006Mmnhtbg qfn ? 24 (pb ? free) 100 / tape & reel NB7VQ1006Mmntxg qfn ? 24 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NB7VQ1006M http://onsemi.com 10 package dimensions qfn24, 4x4, 0.5p case 485l ? 01 issue a notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. seating plane d b 0.15 c a2 a a3 a e pin 1 identification 2x 0.15 c 2x 0.08 c 0.10 c a1 c dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a2 0.60 0.80 a3 0.20 ref b 0.20 0.30 d 4.00 bsc d2 2.70 2.90 e 4.00 bsc e2 2.70 2.90 e 0.50 bsc l 0.30 0.50 24x l d2 b 1 6 7 18 13 19 e 12 e2 e 24 0.10 b 0.05 a c c ref on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NB7VQ1006M/d gigacomm is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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